The raster scan display is commonly utilized both in computer systems and in commercial televisions. An image displayed on the screen comprises an array of pixels arranged in rows and columns. The screen is usually refreshed sequentially row by row from top to bottom. Presently, the refresh rate is usually not lower than 30 Hz. A frame buffer stores the screen refresh data. When any datum in the frame buffer is updated, and the screen is refreshed, the corresponding pixel on the screen is changed.
FIG. 1 schematically illustrates a conventional raster display system. The display system 10 is utilized to display an image on the CRT screen 12. Data which is displayed on the screen 12 is stored in a frame buffer 14. In the conventional display system 10 of FIG. 1, the frame buffer 14 is a dynamic RAM (DRAM).
When the host computer 16 is ready to refresh the DRAM 14, an address is sent to the DRAM 14 from the host computer 16 via the address bus 15 and the multiplexer (MUX) 18. Data to be entered in the DRAM is sent from the host computer 16 to the random port 20 of the DRAM 14 via the bus 30.
To perform a screen refresh operation, an address is sent from the graphic controller 22 to the DRAM 14 via the bus 17 and the multiplexer 18. The data to be transmitted to the screen 12 in the screen refresh operation is read out of the DRAM 14 at the random port 20 and is transmitted via the bus 30 to the shift register 24 which serves as a parallel-to-serial converter. The data is converted from digital to analog form using the Digital-to-Analog converter (DAC) 26 and then transmitted to the screen 12. The timing of the shift register 24 is controlled by a video timing signal generated by the graphic controller 22 and transmitted to the shift register 24 via the line 19. The graphic controller 22 is connected to the host computer 16 via the bus 11 and also generates the vertical synchronization signal (VSYNC), the horizontal synchronization signal (HSYNC), the horizontal blank signal (HBLANK), the vertical blank signal (VBLANK), the horizontal display enable signal (HDE) and the vertical display enable signal (VDE) which are transmitted via lines 21-21a to the screen 12 and the DAC 26.
The display system 10 of FIG. 1 has a significant disadvantage. The major problem is that the bus 30 leading to and from the random port 20 is utilized to receive data from the host computer 16 for frame buffer refresh and to transmit data to the screen 12 for screen refresh. As is known, an increase in screen resolution will increase the time to do a screen refresh. When the time to do a screen refresh reaches a certain level, the host computer 16 will not be able to gain control over the bus 30 and random port 20 to perform frame buffer refresh operations. This conflict over use of the random port 20 and bus 30 results in a decrease in the efficiency of operation of the display system.
One way to avoid this kind of conflict is to implement the frame buffer as a video RAM (VRAM) instead of a simple DRAM. a VRAM 40 is illustrated in FIG. 2. The VRAM 40 of FIG. 2 comprises a DRAM array 42 with a random port 44. The VRAM 40 also has a serial port 45. The serial port 45 is illustratively formed by a shift register 46. An entire row of data from the DRAM 42 is transferred to the serial data register 46 via lines 47 by an operation which is called a read data transfer (RDT). The serial port 45 also includes a register select circuit 43 for implementing a tap pointer which counts synchronously with a serial clock 48. When a read data transfer operation is carried out, an initial value of the tap pointer is also specified. Then starting from the position in the serial data register 46 determined by the initial value of the tap pointer, data is serially transmitted out from the register 46 via the serial I/O 49.
FIG. 3 illustrates a video display system 10'. The system 10' of FIG. 3 is similar to the system 10 of FIG. 1. The differences are that the frame buffer is now implemented by the VRAM 40 instead of the DRAM 14 as in FIG. 1. In addition, the parallel-to-serial converter 24 is eliminated. In the system 10' of FIG. 3, a frame buffer refresh operation transfers data from the host computer 16 to the random port 44 of the VRAM 40 via the bus 47. On the other hand, to carry out a screen refresh operation, data is transferred from the serial port 45 in bit serial format to the DAC 26 for conversion to analog form for refreshing the display on the screen 12. In the display system 10', the serial clock for use by the serial port 45 of the VRAM 40 is supplied by the graphic controller 22 via the line 48.
In short, in the system 10' of FIG. 3, frame buffer refresh operations and screen refresh operations take place via different ports and utilize different buses, so that the two processes are isolated from each other. Therefore conflict between the two types of operations over access to the random port 20 and bus 30 of FIG. 1 are substantially resolved.
The problem with the system 10', of FIG. 3 is that the VRAM 40 utilized therein makes very inefficient use of memory capacity. This is illustrated through use of the following example. Consider the case where the screen 12 has a resolution of 1280 rows with 1600 pixels per row. The pixels in each screen row are labeled 0,1, . . . , 1599. The rows are labeled 0,1, . . . , 1279. The memory arrays 142 of a 256*4 VRAM for storing one 1280*1600 frame of pixels for a screen with this format are illustrated in FIG. 4A.
The memory capacity of FIG. 4A is divided into two banks, labeled BANK 0 and BANK 1. Each bank comprises eight memory arrays. The memory arrays of BANK 0 are labeled 1,2,3,4,5,6,7,8. Similarly, the memory arrays of BANK 1 are labeled 1,2,3,4,5,6,7,8. Each memory array is 2.sup.9 .times.2.sup.9 which means that it has 512 rows and 512 columns locations per row. The 512 rows of each memory array are labeled 0,1, . . . in FIG. 4A. The 512 columns of each memory array are labeled 0,1, . . . , 199, . . . , 256, . . . , in FIG. 4A. The pixels 0,1,2,3 . . . , 1599 of the row 0 of one frame for the screen 12 ar stored in the memory of FIG. 3 as follows. Pixels, 0,8, . . . , 1592 of row 0 of the display screen frame occupy column locations 0,1, . . . , 199 of row 0 of the first memory array in BANK 0. Pixels 1,9, . . . , 1593 of row 0 of the display screen frame occupy column locations 0,1, . . . , 199 of row 0 of the second memory array in BANK 0. Pixels 2,10, . . . 1594 of row 0 of the display screen frame occupy column locations 0,1, . . . , 199 of row 0 of the third memory array of BANK 0. Pixels 7,15, . . . , 1599 of row 0 of the display screen frame occupy column locations 0,1, . . . , 199 of row 0 of the eighth memory array of BANK 0.
In a similar manner, pixels 0,8, . . . , 1592 of row 1 of the display screen frame occupy column locations 256,257, . . . 455 of row 0 of memory array 1 of BANK 0. Pixels 1,9, . . . , 1593 of row 1 of the display screen frame occupy column locations 256, 257, . . . , 455 of row 0 of memory array 2 of BANK 0. Pixels 7,15, . . . , 1599 of row 1 of the frame occupy pixel locations 256, 257 . . . 455 of row 0 of the memory array 8 of BANK 0.
In a similar manner, pixels 0,8, . . . , 1592 of row 2 of the display screen frame occupy column locations 0,1, . . . ,1 99 of row 1 of memory array 1 of BANK 0. Pixels 0,8, . . . , 1592 of row 3 of the screen display occupy column locations 256,257, . . . 455 of row 1 of memory array 1 of BANK 0.
FIG. 4B illustrates in general where particular screen rows are stored in the memory BANKS 0 and 1. The BANK 0 stores pixels for the screen rows 0,1, . . . , 1023 and the BANK 1 stores pixels for the screen rows 1024, . . . , 1279. Each VRAM row stores pixels belonging to two screen rows, the pixels from the even numbered screen rows are stored in the left-hand half of the VRAM memory array and the pixels from the odd numbered screen rows are stored in the right-hand half of the VRAM memory array.
Data is transmitted to the screen 12 of FIG. 3 from the memory of FIGS. 4A and 4B as follows. To display the screen row 0, during a vertical blanking interval, the row 0 of each memory plane in BANK 0 is transferred to the serial port in a read data transfer operation with an initial tap value zero. The data in the serial port is then transferred in bit serial format to the screen. During the horizontal blanking interval following the display of the screen row 0, the row 0 of each memory plane in BANK 0 is again transferred to the serial port, this time with a tap value of 256. The data stored at positions 256, 257, . . . in the serial port is then transferred serially to the screen to refresh row 1 of the screen display. Then row 2 and then row 3 of the screen display are refreshed in the same manner. The process continues until the last row in the screen is refreshed.
As seen from the example of FIG. 4A and FIG. 4B, the VRAM wastes a significant amount of memory space. For a screen resolution comprising 1280 rows*1600 columns, 112 spaces in each VRAM row are empty. On the other hand a different screen resolution may not be able to make use of the memory architecture at all. For example, if a screen row requires more than 256 spaces, the memory apparatus of FIGS. 4A and 4B cannot be utilized.
In view of the foregoing, it is an object of the present invention to provide a display system which makes more efficient use of memory resources.
It is also an object of the invention to provide a display system whose structure is independent of a specific screen resolution.